Vertical transport field-effect transistor (VTFET) devices have potential advantages over conventional FinFETs in terms of density, power consumption, and integration. However, the lack of strain in the channel of VTFET devices makes it difficult to compete with other device options in terms of performance.
Forming channel strain in VTFET devices is extremely challenging. The challenge is due to the free-standing fin channel-based structure of the VTFET devices which makes controlling strain in the vertical fin channel difficult.
Accordingly, techniques for forming (compressive and tensile) strain in VTFET devices would be desirable.